In current asynchronous systems, to obtain higher rate signals, the system must multiplex the signal at each level of the transmission hierarchy. For example, DS1 signals are multiplexed into DS2, then DS2 to DS3, then DS3 to proprietary optical rates. In SDH/SONET, multiplexing is done in one step, since the signal is synchronous.

The second major advantage is cross-connect and add-drop capability. In order to obtain a DS1 or El in current asynchronous systems, the entire signal must be de-multiplexed. The optical rate must be de-multiplexed to a DS3, the DS3 to a DS2, the DS2 to a DS1 or E1. You must obtain all DS1s or E1s in order to obtain a single one. In SDH/SONET the DS1 or E1 can be obtained directly without de-multiplexing the entire signal.

SDH Multiplexing

The 155.520 Mbps Synchronous Transport Module - Level 1 (STM-1) is the basic rate for SDH. All lower rate payloads, such as DS1, El, and DS3, are mapped into an STM-1. Higher rate signals are obtained by multiplexing N STM-1s into an STM-N. No additional overhead or processing is used to create an STM-N from STM-1 signals. The STM-1 signal is composed of either three Administrative Unit Level 3 (AU-3) signals or one AU-4 signal.

Payloads may be mapped into SDH in several ways. A DS1 or El signal is first mapped into a Virtual Container (VC-11, VC-12, respectively). This VC contains the payload plus over-head information. The VC-11 or VC-12 is then mapped into a higher rate VC, such as VC-3, which can also be used to carry DS3 signals. The VC-3 signal has additional overhead information. The higher rate VC is then mapped into the AU-3 or AU-4 signal of which the STM-1 is comprised.

SONET Multiplexing

SONET is similar to SDH, but it uses different building blocks for its transport [5]. The 51.84 Mbps Synchronous Transport Signal - Level 1 is the basic building block of SONET. Lower rate payloads are mapped into STS-1. Multiple STS blocks are multiplexed to form an STS-N.

In SONET, DS1 payloads are first mapped into Virtual Tributaries, called VT1.5. The VI's are similar to the SDH VC in that they contain the payload plus overhead information. The VT1.5s are then mapped into the STS-1 SPE. DS3 payloads are mapped directly into an STS-1 SPE.

Pointers and Pointer Adjustments

Both SDH and SONET utilize payload pointers to carry the signal. The payload pointer gives the location of the beginning of the payload within the SDH/SONET structure.

Differences in phase and frequency between two SDH/SONET NEs (Network Elements) can be handled by the use of payload pointers. If the sending SDH/SONET NE is faster than the receiving NE, the receiving NE will introduce a negative pointer adjustment and shift the payload ahead by one byte or 8 bits. In this manner, the receiving NE can keep up with the sending NE without loss of information. Similarly, if the sending NE is slower than the receiving NE a positive pointer adjustment of one byte is introduced.

Payload Mapping

DS3 signals are mapped into SDH/SONET by using stuffing bits to account for the variations in timing between the DS3 and the SDH/SONET system.

DS1 and E1 signals can be mapped using one of four methods [4, 5, 6]: Asynchronous mapping, Floating Byte Synchronous mapping, Locked Byte Synchronous mapping, and Bit Synchronous mapping.

In asynchronous mapping, the DS1 or El signal is mapped into the VT1.5 or VC-12/13 asynchronously using stuff bits to accommodate timing differences. Pointers are used to indicate the beginning of the VTNC frame. With asynchronous mapping, the DS1 or E1 signal is transported without slips and without retiming of the signal. It will, however, be subject to pointer adjustments which occur due to any frequency differences between SDH/SONET NE in the transmission path.

Floating byte synchronous mapping differs from asynchronous mapping in that it does not include stuff bits to accommodate timing differences between the payload and the NE. This mapping allows direct access to DS0 signals. However, it requires that the DS1 or E1 be locked to the SDH/SONET NE. Any frequency difference between the incoming payload and the first SDH/SONET NE in the transport will cause slips.

Locked byte synchronous mapping does not allow for any stuff bits or pointers in the mapping process. Therefore, the DS1 or E1 must be locked to the SDH/SONET NE. A slip buffer must be provided to accommodate timing differences throughout the transport.

Bit synchronous mapping is the same as locked byte synchronous mapping except that it does not assume that the DS1 or E1 structure is organized into DS0s. The DS1 or E1 is passed as a single bit stream with or without DS0 or DS1/E1 frames. It is expected that the majority of networks will use asynchronous mapping to transport DS1 and E1 signals.

Pointer adjustments occur when the sending SDH/SONET Network Element's (NE's) timing is different than the receiving SDH/SONET NE's timing. The synchronization performance at any one element in a network is typically characterized by three components: the accuracy of the master clock, the performance of the facilities distributing the reference, and the performance of the receiver clocks obtaining a reference over the facilities. The synchronization inaccuracy of the master clock usually contributes a small portion of the timing inaccuracies in a synchronization network. Synchronization performance is dominated by a combination of the facility and receiver clock performance.

The receiver clock performance can be characterized by its operation in three scenarios:
− Ideal Operation
− Stressed Operation
− Holdover Operation

Ideal operation describes the short-term behavior of the clock and is important to control pointer adjustments in SDH and SONET networks. Stressed operation is the typical mode of operation of a receiver clock, where a receiver clock is expected to receive timing from a source clock over a facility that has short-term impairments. Finally, holdover operation characterizes the clock's performance in the rare case when all tuning references to the clock are lost.

The major sources of pointer adjustments correlate with these modes of clock operation. Under ideal operation, the clock produces random phase movements which greatly contributes to DS3 pointer adjustments. Stress operation of network clocks causes an accumulation of phase errors in a network which can be a major cause of DS1 and El pointer adjustments. Lastly, holdover operation will cause a steady stream of DS3, El, and DS1 periodic pointers.

Ideal Operation and Random Phase Movements

In ideal operation, the receiver clock experiences no interruptions of the input timing reference. Even though this is not typical of real network operation, understanding a clock's performance under ideal operation gives bounds for the clock's performance. It also indicates the short-term noise of a clock, which will impact the occurrence of DS3 pointer adjustments in SDH/SONET networks and the resulting SDH/SONET DS3 payload jitter.

Stressed Operation

This category of operation reflects the performance of a receiver clock under actual network conditions where short interruptions of the timing reference can be expected. The number of interruptions can range from 1 to 100 per day.

All interruptions will affect the receiver clock. During the interruption, the timing reference cannot be used. When reference is restored or if the interruption persists and the clock switches references, there is some error regarding the actual time difference between the local receiver clock and the newly restored reference. The timing error that occurs due to each interruption depends on the clock design, but it should be less than 1 microsecond.

A timing error of 1 microsecond can cause up to seven DS3 pointer adjustments. These seven pointer adjustments can occur in a very short period of time. The SDH/SONET NE is designed to handle this without introducing errors on the payload DS3.

A single stress event will not affect DS1 or El transport through SDH/SONET, since 4.6 and 3.5 microseconds of timing error are required to cause DS1 or El pointer adjustments, respectively. Unfortunately, the timing errors due to stress will accumulate. This accumulation of timing errors is a major cause of DS1 or El pointers.

Holdover Operation

A receiver clock will operate in holdover in the rare case that it loses all its timing references for a significant period of time. There are two main contributors to holdover performance: initial frequency offset and frequency drift. Initial frequency offset is caused by the settability of the local oscillator frequency and the noise on the timing reference when the clock first enters holdover. Frequency drift occurs due to aging of the quartz oscillators.

If the SDH/SONET NE is in holdover or locked to another clock that is in holdover, there will be a steady accumulation of phase errors. In this case, a steady stream of pointer adjustments will occur. The rate at which these pointer adjustments occur will increase as the frequency of the holdover clock drifts.

SDH/SONET can affect DS3 transport, even though it is asynchronous. This is due to the payload pointer adjustments. A change in payload pointer reflects a change in the position of the payload by one byte or 8 UI. (A UI, or unit interval, is the duration of time needed to send a single bit.) This is incompatible with current DS3 systems since they are designed to accept only 5 UI of jitter. Only 5 UI of sudden phase movement are allowed on the input to DS3 equipment. If this 5-UI specification is exceeded, the DS3 equipment may not be able to read the data input and will cause an error in transmission.

It is necessary for the SDH and SONET equipment to slow down (filter) the phase movement caused by a pointer adjustment so that the receiving DS3 equipment can accept the signal without error. However, if the SDH/SONET equipment slows down the phase movement too much, it may begin to overlap with the phase movement caused by the next pointer adjustment. Engineering an SDH/SONET network requires that limiting the occurrence of pointer adjustments be balanced against restricting the SDH/SONET filtering requirements. The former places demands and expense on the network synchronization performance; the latter puts the demands and expense on the SDH/SONET equipment.

As a general trend, ANSI has been specifying SONET insofar as it will •work in current networks with minimal changes. Therefore, it has been placing more demands on the SONET equipment. ETSI and ITU, in general, have taken a slightly different approach and placed fewer synchronization demands on the SDH equipment and more on the network.

Amount of Pointer Adjustments in a Network

The number of pointer adjustments in the network can be understood by considering operation in the three scenarios - ideal, stress, and holdover operations.

Under ideal operation, all clocks in the synchronization network exhibit some random phase movement. Simulations have been done based on typical random phase movement measured in telecommunication networks. They have shown that pointer adjustments on DS3 payloads can occur every 20 to 100 seconds. The number of DS3 pointer adjustments is highly dependent on the short-term (less than 1,000 second) timing stability in the network. In addition, it was found that there could be up to three pointer adjustments occurring simultaneously.

A second major cause of timing inaccuracy is stressed operation on network clocks and the resulting clock rearrangements. The timing error caused by a clock rearrangement is limited to 1 microsecond. However, such a phase movement can cause up to seven DS3 pointer adjustments. These seven pointer adjustments can occur in a very short period of time. The SDH/SONET NE must be able to spread these adjustments out so that the DS3 payload leaving the NE does not experience more than 5 UI of jitter. The number of such events can range from 1 to 100 per day, depending on the network architecture and facility performance.

Clock holdover is a third cause of timing inaccuracies between clocks. With a clock in holdover, the clock's timing will drift from the timing of the network. This will cause a steady stream of pointer adjustments to occur on the payload. For SONET NEs, pointer adjustments may occur every 34 milliseconds when the NE is in holdover. For SDH NE, they occur every 320 milliseconds.

Jitter Introduced by SDH/SONET on Payload DS3s

In order to maintain the 5-UI jitter requirement on DS3 payloads, ANSI has specified the amount of jitter that SONET introduces on the payload.

Table 1, ANSI 053 Jitter Requirements for SONET Interfaces

The effect of SDH/SONET on payload DS1s and E1s is different than its impact on DS3 signals. A pointer adjustment on a DS1 or E1 causes an 8 UI change of phase. This, like the DS3 case, is inconsistent with the requirement that DS1 and E1 equipment are designed to accept 5 UI of jitter. Therefore, the SDH/SONET equipment must slow down (filter) the pointer adjustment. The difference in the DS1 and E1 case is that DS1/E1 pointer adjustments do not occur often. Therefore, it is relatively easy to slow down one pointer adjustment without having it overlap with the occurrence of the next pointer adjustment.

An additional concern with DS1 and E1 payload through SDH/SONET is the wander that can occur. The accumulation of pointer adjustment events over time will cause wander on the payload DS1/E1. This is not a concern in the DS3 case, since DS3s are transmitted asynchronously.

Amount of DS1/E1 Pointer Adjustments in the Network

As with the DS3 pointer adjustment case, the number of DS1/E1 pointer adjustments is given by the three scenarios of Section III: ideal, stress, and holdover operations. Simulations, based on random clock phase movement of clocks in ideal operation, has shown that DS1 pointer adjustments are expected to occur every 1,200 to 8,000 seconds on the DS1 payload. This is so seldom that it is unlikely for two pointer adjustments to occur at the same time.

Since clock rearrangements cause 1 microsecond of phase error or less, it takes several such events to accumulate enough phase error for a DS1 or E1 pointer adjustment. A DS1 pointer adjustment reflects 4.6 micro-seconds of timing difference, whereas E1 pointer adjustments are 3.5 microseconds. The number of DS1/E1 pointer adjustments caused by stress conditions is dependent on the number of clock rearrangements in the network. This, in turn, is highly dependent on network architecture, clock performance, and facility performance. The number of clock rearrangements can range from less than one per day to hundreds per day. Even in situations where the number of rearrangements is large, DS1/E1 pointer adjustments will occur as discrete individual events.

In clock holdover, even the worst network clock (stratum 3) will cause only one pointer adjustment every 12 seconds for a DS1 payload and every nine seconds for Els. An SDH or SONET network element in holdover will cause a DS1 (E1) pointer adjustment every nine (seven) seconds. These are seldom enough that the adjustments will again appear as discrete individual events.

Jitter Introduced by SDH/SONET on Payload DS1s and E1s

In order to maintain the 5-UI jitter requirement on DS3 payloads, ANSI has specified the amount of jitter that SONET introduces on the payload. A portion of the 5 UI jitter into DS1 and E1 equipment will be caused by asynchronous DS3 transport in the network. ANSI allows 2.5 UI of jitter for the asynchronous portion of the transport. The remaining 2.5 UI is allocated for SONET transport.

Table 2. ANSI DS1 Jitter Requirements for SONET Interfaces

Table 3. ANSI Daily D51 Transport Wander Budget

The focus of synchronization planning is the determination of timing distribution and the selection of clocks and facilities used to time the network. The distribution of timing and the selection of clocks are different between SDH and SONET networks. Therefore, this section will consider the synchronization planning needs of SDH networks.

Reference Distribution

ITU provides a synchronization network reference connection as a guideline for synchronization distribution. In the chain, there should be no more than 10 transit or local nodes. These nodes refer to 10 offices that utilize a transit or local level clock as the SSU. Between offices are chains of SDH network element (NE) clocks. No one chain of SDH NE clocks should exceed 20 in number. The total number of SDH NE clocks in the entire reference connection should be less than 60. Each clock in the chain receives timing from the optical carrier.

This reference connection was determined based on simulations of operation under ideal conditions. It should meet the needs for maintaining 5UI jitter levels for DS3, DS1, and E1 transport. Practical measurements have not been done to verify the simulations. It should be noted that the wander introduced on DS1 and E1 transport was not considered in this reference connection. The need to reduce wander levels by limiting stress operation performance may require a change to the reference connection as discussed in the previous section. Also, reliability concerns may require the length of the chain to be shortened.

SSU Clock Requirements

To meet the jitter requirements of DS3, DS1, and E1 transport through SDH, the SSU clock used to time the office in an SDH network should be at the transit or local level. The clock should have low intrinsic noise and should have a filter bandwidth of no more than 0.1 Hz to filter network noise. The clock is also required to have a rearrangement MTIE of 1,000 ns with a phase slope of less than 5 x l0-8 for most of its rearrangement period. This phase slope is considerably less than the phase slope requirements of SONET-based network clocks.

To limit E1 and DS1 wander, an SSU clock with considerably better rearrangement MTIE and increased filtering should be used. ITU has not yet developed guidelines for meeting DS1/E1 wander needs.

SDH Network Element Clocking Requirements

The SDH network element (NE) clock is a poorer performing clock than the ITU local level clock. It has a holdover requirement of 5 x 10-8 for initial frequency offset and 5 x 10-7 per day for frequency drift. Its clock rearrangement requirements are an MTIE of less than 1.0 microseconds with a phase slope of less than 5 x le for most of its rearrangement period.

A major difference between the SDH NE clock and the SSU clock is the bandwidth of its design. The SDH NE clock has a bandwidth of 1 to 10 Hz. It is limited to this range for two reasons. First, the bandwidth must be at least 10 times the bandwidth of the SSU clock so that wander accumulation under ideal operating conditions is minimized. Second, the NE clock must support fast synchronization rearrangements.

When the SDH NEs are configured in a ring and a facility carrying synchronization is interrupted , the synchronization distribution in the ring is reconfigured. The entire ring of 20 SDH NEs must reconfigure its synchronization distribution in about 15 seconds. This requires that each NE must reconfigure its synchronization and have a stable output within about one second. The one-second stability requirement limits how slowly the SDH NE can react, and hence, limits its filtering bandwidth.

Synchronization planning involves the determination of timing reference distribution and the selection of clocks and facilities used in the synchronization network.

Reference Distribution

Synchronization distribution in SONET-based networks is different from distribution in SDH networks. In SONET networks, there are no SONET network elements (NEs) in the synchronization chain. The typical synchronization plan is given in Figure 9. The length of the synchronization chain is not specified by ANSI. However, most administrations will keep the synchronization chains short, with chain lengths of 1 to 6 being typical.

This synchronization network configuration, in conjunction with BITS and SONET NE clocks described in the following sections, should support error-free transmission of DS3, DS1, and E1 payloads.

BITS Clocks Requirements

The BITS clock needs to meet several requirements if it is to support SONET transport. First, the band-limited short-term noise should not exceed 17 nanoseconds. Second, the BITS clock must filter noise below 100 seconds, as is implied by the ANSI output noise requirements. Third, to support DS1/E1 transport, the BITS clock requires low daily wander, implying that the BITS clock has excellent phase buildout and low MTIE during rearrangement.

To meet these requirements, it is recommended that the BITS clock be at the stratum 2 or 3E level and have exceptional rearrangement MTIE. The stratum 3E clock is a new clock, introduced by Bellcore to meet the needs of SONET networks. A stratum 3E clock is between a stratum 2 and 3 in performance. It has the required noise filtering capabilities, a rearrangement MTIE of 100ns, and the holdover capability of an ITU local clock. This clock is currently not accepted as a standard by ANSI. It does, however, provide a useful guideline for the minimum level of performance needed from a BITS clock.

SONET Network Element Clocking Requirements

The clock in a SONET network element (NE) differs from the SDH NE clock primarily in its noise filtering. The SONET NE clock has a filtering bandwidth of 0.1 Hz, as compared to the 1 - 10 Hz bandwidth of the SDH NE clock. This is needed to filter the quicker phase transients of the BITS clocks (as compared to those of the SSU clock) and to filter network noise.

The SONET NE does not have the speed restriction of SDH. The synchronization rearrangement for a ring of 16 SONET NEs can occur over a 5-minute period. Similar to the SDH NE clock, the SONET NE has a holdover requirement of 5 x 10-8 for initial frequency offset and 5 x 10-7 per day for frequency drift. The SONET NE also has a clock rearrangement requirement of less than 1.0 microseconds MTIE with a phase slope of less than 9 x 10-7 for the first 0.5 seconds and 3 x 10-7 thereafter. Note that this phase slope is more lenient than that for SDH NE clocks.